Sr. Staff Verification Engineer
8+ years in IC design verification; B.S. or M.S. in Electrical/Computer Engineering; SystemVerilog/UVM; RTL/AMS verification; scripting (Python/Perl); strong leadership and communication.
Key Responsibilities
- define verification
- design testbenches
- mentor engineers
Skills & Tools
SystemVerilog, UVM, Verilog, VHDL, Python, Perl, Synopsys, reputed company, reputed company
Job Details
- Category: Engineering
- Seniority: Senior Level
- Commitment: Full Time
- Workplace: Remote — Hyderabad, Telangana, India
- Languages: English
About reputed company
A global provider of semiconductor and IoT connectivity solutions. — Industry: Information Technology
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