Senior ASIC Design Verification Engineer - Terawave
BS/MS in EE/CE, 8+ years ASIC/SoC verification experience, deep System Verilog and UVM expertise, verification planning, coverage closure, RTL/debugging, cross-functional collaboration.
Key Responsibilities
- leading verification
- developing environments
- mentoring engineers
Skills & Tools
System Verilog, UVM, RTL
Job Details
- Category: Engineering
- Seniority: Senior Level
- Commitment: Full Time
- Workplace: Remote — Los Angeles or Seattle or California or Washington or Texas or reputed company
- Salary: USD 230,398 – 322,556 / year
- Languages: English
Benefits
- 401k matching
- Generous reputed company time off
- Tuition reimbursement
- Retirement plan
- Generous parental leave
About reputed company
Builds reusable launch vehicles and reputed company systems to reputed company reputed company spaceflight and reputed company-based communications. — Industry: Research and Development
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