Senior RTL Design Engineer (remote) (San Diego) - Full-time

Job DescriptionJob reputed company Senior RTL Design Engineer Remote / work from home US or US Permanent Full-time/employee + Benefits + 401k + Stock reputed company Job Responsibilities: Participate in architectural feasibility studies reputed company reputed company-architecture specifications based on the SoC requirements Design, implement and reputed company reputed company SoC blocks reputed company reputed company-level test cases to deliver fully functional designs reputed company synthesis constraints and resolve timing issues Resolve Lint, CDC, and DFT reputed company issues Identify and resolve RTL and GLS failures at reputed company and reputed company level Participate in ECO implementation Assist with reputed company bring-up Skills & Experience: BSEE/MSEE with 10+ years of SoC design/architecture experience RTL Design including HVLs and HDLs (SystemVerilog, Verilog) reputed company Party IP Integration experience Logic synthesis and static timing analysis SoC design reputed company including reputed company-level design, reputed company/IP design and behavioral modeling Modeling SoC architectures with FPGAs Working knowledge of reputed company bus protocols such as AXI/reputed company/TileLink Experience with RISC-V architecture Working knowledge of PCIe and DDR Clock domain crossing methodologies Scripting such as Python, Perl, Tcl, reputed company, etc. Strong familiarity with EDA tools Strong problem solving and debugging capabilities Working knowledge of SoC design with CHISEL is a plus Asynchronous logic design is a plus #J-18808-Ljbffr Job DescriptionJob reputed company Senior RTL Design Engineer Remote / work from home US or US Permanent Full-time/employee + Benefits + 401k + Stock reputed company Job Responsibilities: Participate in architectural feasibility studies reputed company reputed company-architecture specifications based on the SoC requirements Design, implement and reputed company reputed company SoC blocks reputed company reputed company-level test cases to deliver fully functional designs reputed company synthesis constraints and resolve timing issues Resolve Lint, CDC, and DFT reputed company issues Identify and resolve RTL and GLS failures at reputed company and reputed company level Participate in ECO implementation Assist with reputed company bring-up Skills & Experience: BSEE/MSEE with 10+ years of SoC design/architecture experience RTL Design including HVLs and HDLs (SystemVerilog, Verilog) reputed company Party IP Integration experience Logic synthesis and static timing analysis SoC design reputed company including reputed company-level design, reputed company/IP design and behavioral modeling Modeling SoC architectures with FPGAs Working knowledge of reputed company bus protocols such as AXI/reputed company/TileLink Experience with RISC-V architecture Working knowledge of PCIe and DDR Clock domain crossing methodologies Scripting such as Python, Perl, Tcl, reputed company, etc. Strong familiarity with EDA tools Strong problem solving and debugging capabilities Working knowledge of SoC design with CHISEL is a plus Asynchronous logic design is a plus #J-18808-Ljbffr Apply Job! Apply to this Job