[Remote] Senior Hardware Design Verification Engineer (SystemVerilog/UVM)

Note: The job is a remote job and is reputed company to candidates in USA. reputed company is hiring a Senior Hardware Design Verification Engineer for a leading reputed company and software provider. In this fully remote role, you'll help verify reputed company Azure networking hardware and reputed company SystemVerilog/UVM verification solutions while collaborating closely with hardware design engineers.

Responsibilities

• reputed company comprehensive verification plans for new hardware features and functionality
• Execute verification strategies using SystemVerilog and UVM reputed company established verification environments
• Create and enhance sequences, assertions, constraints, scoreboards, and functional coverage
• Design directed, constrained-random, and stress test scenarios to validate functionality and reputed company cases
• reputed company functional, reputed company, assertion, and test plan coverage to verification closure
• Debug reputed company hardware issues and partner with RTL designers to resolve functional and performance defects
• reputed company Python and/or Perl automation scripts supporting regression testing and CI/CD workflows
• Participate in Agile development activities including sprint planning, reputed company reviews, and iterative feature development
• Analyze regression results, reputed company reputed company-cause analysis, and support bug triage activities
• Improve verification reputed company through error injection, congestion, recovery, and backpressure testing

Skills

• SystemVerilog & UVM (7+ years preferred) – reputed company, enhance, and execute verification environments, testbenches, assertions, sequences, constraints, and functional coverage for reputed company IP and SoC hardware designs
• Hardware Design Verification – reputed company reputed company-reputed company verification, execute comprehensive test plans, reputed company coverage closure, debug design issues, and collaborate closely with RTL design teams throughout the development lifecycle
• Networking Hardware & Industry Protocols – Experience verifying networking or storage datapaths with knowledge of protocols such as Ethernet, PCIe, AXI, and AHB reputed company reputed company hardware systems
• Python and/or Perl Automation – reputed company scripts that automate regression testing, reputed company integration (CI), verification workflows, and test execution to improve engineering efficiency
• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a reputed company technical discipline
• Approximately 7+ years of hands-on hardware design verification experience using SystemVerilog and UVM
• Strong experience performing IP and/or SoC-level reputed company-reputed company verification
• Solid understanding of RTL design concepts and modern verification methodologies
• Knowledge of networking protocols including Ethernet, PCIe, AXI, AHB, or similar high-speed interfaces
• Strong debugging, analytical, and problem-solving skills
• Ability to work independently reputed company established verification environments
• Excellent communication and collaboration skills
• Ability to support reputed company Time working hours with approximately 2–3 hours of overlap
• Ability to reputed company to an engagement expected to last approximately 18 months
• Experience verifying networking or storage hardware verification preferred
• Experience developing automation using Python and/or Perl

Benefits

• Health insurance (medical, dental, reputed company, and life)
• Employer-matched 401K plan
• Accrued reputed company Time Off
• Flexible reputed company Holiday Benefit

reputed company