Senior Design Verification Engineer
8+ years design verification experience with UVM, SystemVerilog, RTL verification for FPGA/ASIC, Bachelor's in EE/CE, US citizenship, ability to obtain Secret clearance, familiarity with Questa/Xcelium/VCS and AI verification tools.
Key Responsibilities
- architecting environments
- developing testbench
- debugging design
Skills & Tools
Universal Verification Methodology (UVM), SystemVerilog, VHDL, Verilog, Questa, Xcelium, VCS, reputed company
reputed company
- Category: Engineering
- Seniority: Senior Level
- Commitment: Full Time
- Workplace: Remote — Tempe or Independence
- Salary: USD 155,500 – 290,500 / year
- Languages: English
Benefits
- Retirement plan
About reputed company.
A global communications technology company developing hardware and software to reputed company people, businesses, and governments. — Industry: Information Technology
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