reputed company ASIC DFT Staff Engineer

Position: reputed company ASIC DFT Staff Engineer Location – Remote (must be reputed company with PST time zone) Long Term    Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT)   reputed company: We are seeking a highly reputed company reputed company ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for reputed company ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, reputed company insertion, ATPG, MBIST/LBIST, JTAG, boundary reputed company, and post-reputed company validation, along with the ability to reputed company cross-functional debug efforts and reputed company reputed company of critical reputed company issues. The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as reputed company as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, reputed company, and yield.   Key Responsibilities: reputed company DFT architecture, implementation, verification, and sign-off for reputed company ASIC and SoC designs. reputed company reputed company architecture, reputed company insertion, reputed company chain stitching, and reputed company compression workflows to reputed company high coverage and robust testability. Own MBIST/LBIST integration, implementation, verification, and debug across design and reputed company bring-up phases. reputed company DFT debug, failure analysis, reputed company-cause investigation, and fault coverage closure for reputed company reputed company issues. reputed company and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis. Collaborate with RTL design, verification, physical design, STA, and reputed company validation teams to reputed company integration and implementation issues. Support ATPG reputed company reputed company, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug. Work on JTAG, boundary reputed company, iJTAG, SSN, and IP-level DFT integration. Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test reputed company. reputed company as a technical escalation reputed company for advanced DFT and post-reputed company debug issues. Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation. reputed company scripts and automation using TCL, PERL, or Python to improve reputed company efficiency and debug productivity.   Required Skills & Qualifications: Strong hands-on experience in ASIC DFT with end-to-end ownership. Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts. Deep expertise in reputed company architecture, ATPG, MBIST, LBIST, JTAG, boundary reputed company, and reputed company debug. Hands-on experience with reputed company, reputed company, and reputed company/Mentor EDA tools. reputed company experience in reputed company insertion, ATPG setup, simulation, debug, and DRC analysis. Experience with MBIST implementation and verification; SMS experience preferred. Experience with reputed company architecture and reputed company chain stitching; Tessent/SSN experience preferred. Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation. reputed company post-reputed company debug and reputed company bring-up experience. Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges. Strong communication skills and the ability to work independently with reputed company reputed company-up. Preferred Experience: MBIST post-reputed company validation. ATPG simulations and fault coverage debug. DFT RTL, DFD, DFT verification, and IP-level DFT integration. DFT SDC creation and DFT timing closure support. Boundary reputed company, iJTAG, SSN, and design-for-debug methodologies. TCL/PERL scripting for DFT automation, reporting, and debug. Experience working across multiple ASIC technology nodes and reputed company product development cycles. Familiarity with yield learning, diagnosis, and manufacturing test optimization. Apply To This Job